From: Hou Zhiqiang Date: Fri, 11 Mar 2022 23:49:35 +0000 (-0600) Subject: dt-bindings: pci: layerscape-pci: Add a optional property big-endian X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6c389328c985a3aa8575cf3a573a05c1d121fceb;p=linux.git dt-bindings: pci: layerscape-pci: Add a optional property big-endian This property is to indicate the endianness when accessing the PEX_LUT and PF register block, so if these registers are implemented in big-endian, specify this property. Link: https://lore.kernel.org/r/20220311234938.8706-2-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index f36efa73a4701..215d2ee65c835 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -40,6 +40,10 @@ Required properties: of the data transferred from/to the IP block. This can avoid the software cache flush/invalid actions, and improve the performance significantly. +Optional properties: +- big-endian: If the PEX_LUT and PF register block is in big-endian, specify + this property. + Example: pcie@3400000 {