From: Joey Gouly Date: Tue, 6 Jun 2023 14:58:57 +0000 (+0100) Subject: arm64: Document boot requirements for PIE X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6c792b7d3c2c901cdd76b760d6676510e83c778d;p=linux.git arm64: Document boot requirements for PIE Features PIE and TCR2 introduce new registers, update the trap requirements for these features. Signed-off-by: Joey Gouly Cc: Will Deacon Cc: Mark Brown Reviewed-by: Mark Brown Reviewed-by: Catalin Marinas Link: https://lore.kernel.org/r/20230606145859.697944-19-joey.gouly@arm.com Signed-off-by: Catalin Marinas --- diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index b3bbf330ed0ab..b57776a68f156 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -385,6 +385,32 @@ Before jumping into the kernel, the following conditions must be met: - HCRX_EL2.MSCEn (bit 11) must be initialised to 0b1. + For CPUs with the Extended Translation Control Register feature (FEAT_TCR2): + + - If EL3 is present: + + - SCR_EL3.TCR2En (bit 43) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HCRX_EL2.TCR2En (bit 14) must be initialised to 0b1. + + For CPUs with the Stage 1 Permission Indirection Extension feature (FEAT_S1PIE): + + - If EL3 is present: + + - SCR_EL3.PIEn (bit 45) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HFGRTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. + + - HFGWTR_EL2.nPIR_EL1 (bit 58) must be initialised to 0b1. + + - HFGRTR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. + + - HFGRWR_EL2.nPIRE0_EL1 (bit 57) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented