From: Konrad Dybcio <konrad.dybcio@linaro.org>
Date: Mon, 12 Feb 2024 13:10:14 +0000 (+0100)
Subject: arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=6e4f7e53991ca7e70dc7d5d9d66c833091e1f6ae;p=linux.git

arm64: dts: qcom: sm8550: Mark DWC3 as dma-coherent

In a fairly new development, Qualcomm somehow made the DWC3 block
cache-coherent. Annotate that.

Fixes: 7f7e5c1b037f ("arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Link: https://lore.kernel.org/r/20240210-topic-1v-v1-6-fda0db38e29b@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index a72627f4d8cd0..5adb9b178b05a 100644
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -3245,6 +3245,7 @@
 				snps,usb2-lpm-disable;
 				snps,has-lpm-erratum;
 				tx-fifo-resize;
+				dma-coherent;
 
 				ports {
 					#address-cells = <1>;