From: Alistair Francis <alistair.francis@wdc.com>
Date: Sat, 1 Feb 2020 01:02:15 +0000 (-0800)
Subject: target/riscv: Set VS bits in mideleg for Hyp extension
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=713d8363deb3774db14fb88a9fcd99687dcef114;p=qemu.git

target/riscv: Set VS bits in mideleg for Hyp extension

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f7333286bd..c0e942684d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -448,6 +448,9 @@ static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
 {
     env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
+    if (riscv_has_ext(env, RVH)) {
+        env->mideleg |= VS_MODE_INTERRUPTS;
+    }
     return 0;
 }