From: Philippe Mathieu-Daudé Date: Fri, 13 Aug 2021 10:36:46 +0000 (+0200) Subject: target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=71ed30b7d4c7bc7d8069eba601d7384e378f3024;p=qemu.git target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr Per the manual '龙芯 GS264 处理器核用户手册' v1.0, chapter 1.1.5 SEGBITS: the 3A1000 (based on GS464 core) implements 48 virtual address bits in each 64-bit segment, not 40. Fixes: af868995e1b ("target/mips: Add Loongson-3 CPU definition") Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Huacai Chen Message-Id: <20210813110149.1432692-3-f4bug@amsat.org> --- diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index c6ab3af190..cbc45fcb0e 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -828,7 +828,7 @@ const mips_def_t mips_defs[] = (0x1 << FCR0_D) | (0x1 << FCR0_S), .CP1_fcr31 = 0, .CP1_fcr31_rw_bitmask = 0xFF83FFFF, - .SEGBITS = 42, + .SEGBITS = 48, .PABITS = 48, .insn_flags = CPU_MIPS64R2 | INSN_LOONGSON3A | ASE_LMMI | ASE_LEXT,