From: Linus Torvalds Date: Tue, 12 Jun 2018 00:57:38 +0000 (-0700) Subject: Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=721afaa2aeb860067decdddadc84ed16f42f2048;p=linux.git Merge tag 'armsoc-dt' of git://git./linux/kernel/git/arm/arm-soc Pull ARM SoC device tree updates from Olof Johansson: "As always, a large number of DT updates. Too many to enumerate them all, but at a glance: New SoCs introduced in this release: - Amlogic: + Meson 8M2 SoC, a.k.a. S812. A quad Cortex-A9 SoC used in some set top boxes and other products. - Mediatek: + MT7623A, which is a flavor of the MT7623 family with other on-chip ethernet options. - Qualcomm: + SDM845, a.k.a Snapdragon 845, an 4+4-core Kryo 385/845 (Cortex-A75/A55 derivative) SoC that's one of the current high-end mobile SoCs. It's great to see mainline support for it. So far, you can't do much with it, since a lot of peripherals are not yet in the DTs but driver support for USB, GPU and other pieces are starting to trickle in. This might end up being a well-supported SoC upstream if the momentum keeps up. - Renesas: + R8A77990, a.k.a R-Car E3, a new automotive entertainment-targeted SoC. Currently only one Cortex-A53 CPU is enabled, we are eagerly awaiting more. So far, basic drivers such as serial, gpios, PMU and ethernet are enabled. + R8A77470, a.k.a. RZ/G1C, a new dual Cortex-A7 SoC with PowerVR GPU. Same here, basic set of drivers such as serial, gpios and ethernet enabled, and SMP support is also forthcoming. - STMicroelectronics: + STM32F469, very similar tih STM32F429 but with display support Enhancements to SoCs/platforms (DTS contents, some driver portions might not be in yet): - Allwinner sun8i (h3/a33/a83t) SMP, DVFS tweaks, misc - Amlogic Meson: I2C, UFS, TDM, GPIO external interrupts, MMC resets - Hisilicon hi3660: Thermal cooling, CPU frequency scaling, mailbox interfaces - Marvell Berlin2CD: SMP support, thermal sensors - Mediatek MT7623: Highspeed DMA, audio support - Qualcomm IPQ8074 PCIe support, MSM8996 UFS support - Renesas: Watchdog and PMU support across many platforms - Rockchip RK3399: USB3 OTG support - Samsung Exynos: Audio-over-HDMI on Odroid X/X2/U3 - STMicro STM32: Lots of peripherals added to STM32MP175C - Uniphier: Ethernet support New boards: - Allwinner A20: Olimex A20-SOM-EVB-eMMC variant - Allwinner H2+: Libre Computer ALL-H3-CC (h2+ version) - Allwinner A33: Nintendo NES/SuperNES Classic Edition - Aspeed: S2600WF, Inventec Lanyang BMC, Portwell Neptune - Berlin2CD: Valve Steam Link - Broadcom BCM5301X: Luxul XAP-1610 and XWR-3150 V1 - Broadcom: Raspberry Pi 3 B+ - Mediatek MT7623N and MT7623A: reference boards - Meson 8M2: Tronsmart MXIII Plus - NXP i.MX: Engicam i.CoreM6, DHCOM iMX6 SOM, BTicino i.MX6DL Mamoj - Qualcomm MSM8974: Sony Xperia Z1 Compact support - Qualcomm SDM845: MTP development board - Renesas: Ebisu R8A77990 board - Renesas RZ/G1C: iwg23s: iWave G235-SDB - TI am335x: Pocketbeagle support" * tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (448 commits) ARM: dts: aspeed: Fix hwrng register address arm64: dts: sprd: whale2: Add the rtc enable clock for watchdog arm64: dts: sprd: Add GPIO and GPIO keys device nodes arm64: dts: sprd: fix typo in 'remote-endpoint' arm64: dts: apq8096-db820c: Removed bt-en-1-8v regulator arm64: dts: fix regulator property name for wlan pcie endpoint arm64: dts: qcom: msm8996: Use UFS_GDSC for UFS ARM: dts: pxa3xx: fix MMC clocks ARM: pxa: dts: add pin definitions for extended GPIOs ARM: pxa: dts: add gpio-ranges to gpio controller ARM: dts: ipq8074: Enable few peripherals for hk01 board ARM: dts: ipq8074: Add pcie nodes ARM: dts: ipq8074: Add peripheral nodes ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c2 board file ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk07.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk07.1 common data ARM: dts: ipq4019: Add qcom-ipq4019-ap.dk04.1-c3 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.1-c1 board file ARM: dts: ipq4019: Add ipq4019-ap.dk04.dtsi ARM: dts: ipq4019: Change the max opp frequency ... --- 721afaa2aeb860067decdddadc84ed16f42f2048 diff --cc arch/arm/boot/dts/logicpd-som-lv.dtsi index 6fa7bba3e8015,1ec1a1f5696a8..3bb28c03ca74e --- a/arch/arm/boot/dts/logicpd-som-lv.dtsi +++ b/arch/arm/boot/dts/logicpd-som-lv.dtsi @@@ -200,9 -227,14 +228,15 @@@ pinctrl-single,pins = < OMAP3_CORE1_IOPAD(0x21ba, PIN_INPUT | MUX_MODE0) /* i2c1_scl.i2c1_scl */ OMAP3_CORE1_IOPAD(0x21bc, PIN_INPUT | MUX_MODE0) /* i2c1_sda.i2c1_sda */ + OMAP3_CORE1_IOPAD(0x20ba, PIN_OUTPUT | MUX_MODE4) /* gpmc_ncs6.gpio_57 */ >; }; + + tsc2004_pins: pinmux_tsc2004_pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2186, PIN_INPUT | MUX_MODE4) /* mcbsp4_dr.gpio_153 */ + >; + }; }; &omap3_pmx_wkup { diff --cc arch/arm/boot/dts/stm32mp157c.dtsi index 4fa0df853c8a9,b66f673b50383..7d17538934538 --- a/arch/arm/boot/dts/stm32mp157c.dtsi +++ b/arch/arm/boot/dts/stm32mp157c.dtsi @@@ -178,18 -489,314 +489,321 @@@ usart6: serial@44003000 { compatible = "st,stm32h7-uart"; reg = <0x44003000 0x400>; - interrupts = ; - clocks = <&clk_pclk1>; + interrupts = ; + clocks = <&rcc USART6_K>; + status = "disabled"; + }; + + timers15: timer@44006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44006000 0x400>; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@44007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44007000 0x400>; + clocks = <&rcc TIM16_K>; + clock-names = "int"; status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@44008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44008000 0x400>; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + + dma1: dma@48000000 { + compatible = "st,stm32-dma"; + reg = <0x48000000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA1>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dma2: dma@48001000 { + compatible = "st,stm32-dma"; + reg = <0x48001000 0x400>; + interrupts = , + , + , + , + , + , + , + ; + clocks = <&rcc DMA2>; + #dma-cells = <4>; + st,mem2mem; + dma-requests = <8>; + }; + + dmamux1: dma-router@48002000 { + compatible = "st,stm32h7-dmamux"; + reg = <0x48002000 0x1c>; + #dma-cells = <3>; + dma-requests = <128>; + dma-masters = <&dma1 &dma2>; + dma-channels = <16>; + clocks = <&rcc DMAMUX>; + }; + + rcc: rcc@50000000 { + compatible = "st,stm32mp1-rcc", "syscon"; + reg = <0x50000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; }; + exti: interrupt-controller@5000d000 { + compatible = "st,stm32mp1-exti", "syscon"; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x5000d000 0x400>; + }; + + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + }; + + vrefbuf: vrefbuf@50025000 { + compatible = "st,stm32-vrefbuf"; + reg = <0x50025000 0x8>; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <2500000>; + clocks = <&rcc VREF>; + status = "disabled"; + }; + + cryp1: cryp@54001000 { + compatible = "st,stm32mp1-cryp"; + reg = <0x54001000 0x400>; + interrupts = ; + clocks = <&rcc CRYP1>; + resets = <&rcc CRYP1_R>; + status = "disabled"; + }; + + rng1: rng@54003000 { + compatible = "st,stm32-rng"; + reg = <0x54003000 0x400>; + clocks = <&rcc RNG1_K>; + resets = <&rcc RNG1_R>; + status = "disabled"; + }; + + mdma1: dma@58000000 { + compatible = "st,stm32h7-mdma"; + reg = <0x58000000 0x1000>; + interrupts = ; + clocks = <&rcc MDMA>; + #dma-cells = <5>; + dma-channels = <32>; + dma-requests = <48>; + }; + + qspi: qspi@58003000 { + compatible = "st,stm32f469-qspi"; + reg = <0x58003000 0x1000>, <0x70000000 0x10000000>; + reg-names = "qspi", "qspi_mm"; + interrupts = ; + clocks = <&rcc QSPI_K>; + resets = <&rcc QSPI_R>; + status = "disabled"; + }; + + crc1: crc@58009000 { + compatible = "st,stm32f7-crc"; + reg = <0x58009000 0x400>; + clocks = <&rcc CRC1>; + status = "disabled"; + }; + + usbh_ohci: usbh-ohci@5800c000 { + compatible = "generic-ohci"; + reg = <0x5800c000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + status = "disabled"; + }; + + usbh_ehci: usbh-ehci@5800d000 { + compatible = "generic-ehci"; + reg = <0x5800d000 0x1000>; + clocks = <&rcc USBH>; + resets = <&rcc USBH_R>; + interrupts = ; + companion = <&usbh_ohci>; + status = "disabled"; + }; + + dsi: dsi@5a000000 { + compatible = "st,stm32-dsi"; + reg = <0x5a000000 0x800>; + clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clock-names = "pclk", "ref", "px_clk"; + resets = <&rcc DSI_R>; + reset-names = "apb"; + status = "disabled"; + }; + + ltdc: display-controller@5a001000 { + compatible = "st,stm32-ltdc"; + reg = <0x5a001000 0x400>; + interrupts = , + ; + clocks = <&rcc LTDC_PX>; + clock-names = "lcd"; + resets = <&rcc LTDC_R>; + status = "disabled"; + }; + + usbphyc: usbphyc@5a006000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc USBPHY_K>; + resets = <&rcc USBPHY_R>; + status = "disabled"; + + usbphyc_port0: usb-phy@0 { + #phy-cells = <0>; + reg = <0>; + }; + + usbphyc_port1: usb-phy@1 { + #phy-cells = <1>; + reg = <1>; + }; + }; + usart1: serial@5c000000 { compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>;