From: Biju Das Date: Tue, 2 Aug 2022 10:15:34 +0000 (+0100) Subject: arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=72a482dbaec4b9e4d54b81be6bdb8c016fd2f4bd;p=linux.git arm64: dts: renesas: r9a07g043: Fix SCI{Rx,Tx} interrupt types As per the RZ/G2UL Hardware User's Manual (Rev.1.00 Apr, 2022), the interrupt type of SCI{Rx,Tx} is edge triggered. Signed-off-by: Biju Das Fixes: cf40c9689e5109bf ("arm64: dts: renesas: Add initial DTSI for RZ/G2UL SoC") Link: https://lore.kernel.org/r/20220802101534.1401342-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi index d1b567d1b6e11..ff6aab388eb7c 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi @@ -340,8 +340,8 @@ compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d000 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI0_CLKP>; @@ -355,8 +355,8 @@ compatible = "renesas,r9a07g043-sci", "renesas,sci"; reg = <0 0x1004d400 0 0x400>; interrupts = , - , - , + , + , ; interrupt-names = "eri", "rxi", "txi", "tei"; clocks = <&cpg CPG_MOD R9A07G043_SCI1_CLKP>;