From: Peter Maydell Date: Tue, 12 Jul 2016 11:34:41 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=74e1b782b34e280b06a90f61fdbac5a046cbe491;p=qemu.git Merge remote-tracking branch 'remotes/lalrae/tags/mips-20160712' into staging MIPS patches 2016-07-12 Changes: * support 10-bit ASIDs * MIPS64R6-generic renamed to I6400 * initial GIC support * implement RESET_BASE register in CM GCR # gpg: Signature made Tue 12 Jul 2016 11:49:50 BST # gpg: using RSA key 0x52118E3C0B29DA6B # gpg: Good signature from "Leon Alrae " # Primary key fingerprint: 8DD3 2F98 5495 9D66 35D4 4FC0 5211 8E3C 0B29 DA6B * remotes/lalrae/tags/mips-20160712: target-mips: enable 10-bit ASIDs in I6400 CPU target-mips: support CP0.Config4.AE bit target-mips: change ASID type to hold more than 8 bits target-mips: add ASID mask field and replace magic values target-mips: replace MIPS64R6-generic with the real I6400 CPU model hw/mips_cmgcr: implement RESET_BASE register in CM GCR hw/mips_cpc: make VP correctly start from the reset vector target-mips: add exception base to MIPS CPU hw/mips/cps: create GIC block inside CPS hw/mips: implement Global Interrupt Controller hw/mips: implement GIC Interval Timer Signed-off-by: Peter Maydell --- 74e1b782b34e280b06a90f61fdbac5a046cbe491