From: Steven Lee Date: Tue, 14 Dec 2021 04:02:38 +0000 (+0800) Subject: gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=75d840c0f5d79b4d71ecb8743ad3e7f82dd206a7;p=linux.git gpio: gpio-aspeed-sgpio: Fix wrong hwirq base in irq handler commit e5a7431f5a2d6dcff7d516ee9d178a3254b17b87 upstream. Each aspeed sgpio bank has 64 gpio pins(32 input pins and 32 output pins). The hwirq base for each sgpio bank should be multiples of 64 rather than multiples of 32. Signed-off-by: Steven Lee Signed-off-by: Bartosz Golaszewski Signed-off-by: Greg Kroah-Hartman --- diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sgpio.c index 3d6ef37a7702a..b3a9b8488f11d 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -395,7 +395,7 @@ static void aspeed_sgpio_irq_handler(struct irq_desc *desc) reg = ioread32(bank_reg(data, bank, reg_irq_status)); for_each_set_bit(p, ®, 32) - generic_handle_domain_irq(gc->irq.domain, i * 32 + p * 2); + generic_handle_domain_irq(gc->irq.domain, (i * 32 + p) * 2); } chained_irq_exit(ic, desc);