From: Anton Blanchard Date: Tue, 25 Mar 2014 02:40:29 +0000 (+1100) Subject: target-ppc: MSR_POW not supported on POWER7/7+/8 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=76ac9940c3114db35df92582f3549d9a64a369c4;p=qemu.git target-ppc: MSR_POW not supported on POWER7/7+/8 Remove MSR_POW from the msr_mask for POWER7/7P/8. Signed-off-by: Anton Blanchard Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Signed-off-by: Andreas Färber --- diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 87c00a1af3..d07e186416 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -7075,7 +7075,7 @@ POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206; - pcc->msr_mask = 0x800000000284FF37ULL; + pcc->msr_mask = 0x800000000280FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -7118,7 +7118,7 @@ POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data) PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206; - pcc->msr_mask = 0x800000000284FF37ULL; + pcc->msr_mask = 0x800000000280FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault; @@ -7175,7 +7175,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data) PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 | PPC2_ISA205 | PPC2_ISA207S; - pcc->msr_mask = 0x800000000284FF37ULL; + pcc->msr_mask = 0x800000000280FF37ULL; pcc->mmu_model = POWERPC_MMU_2_06; #if defined(CONFIG_SOFTMMU) pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;