From: Tudor Ambarus Date: Thu, 9 Dec 2021 12:29:39 +0000 (+0200) Subject: spi: atmel,quadspi: Define sama7g5 QSPI X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=77850bda360dd9b389d5064c64b79467d613c3d6;p=linux.git spi: atmel,quadspi: Define sama7g5 QSPI sama7g5 embedds 2 instances of the QSPI controller: 1/ One Octal Serial Peripheral Interface (QSPI0) Supporting up to 200 MHz DDR. Octal, TwinQuad, HyperFlash and OctaFlash Protocols Supported 2/ One Quad Serial Peripheral Interface (QSPI1) Supporting Up to 90 MHz DDR/133 MHz SDR Signed-off-by: Tudor Ambarus Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20211209122939.339810-3-tudor.ambarus@microchip.com Signed-off-by: Mark Brown --- diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 7d0408f53c5fe..1d493add4053d 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -17,6 +17,8 @@ properties: enum: - atmel,sama5d2-qspi - microchip,sam9x60-qspi + - microchip,sama7g5-qspi + - microchip,sama7g5-ospi reg: items: @@ -32,17 +34,27 @@ properties: minItems: 1 items: - description: peripheral clock - - description: system clock, if available + - description: system clock or generic clock, if available clock-names: minItems: 1 items: - const: pclk - - const: qspick + - enum: [ qspick, gclk ] interrupts: maxItems: 1 + dmas: + items: + - description: tx DMA channel + - description: rx DMA channel + + dma-names: + items: + - const: tx + - const: rx + '#address-cells': const: 1