From: Anton Kochkov <anton.kochkov@proton.me>
Date: Thu, 12 Jan 2023 14:24:02 +0000 (+0000)
Subject: target/tricore: Fix OPC1_16_SRO_LD_H translation
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=77eb0085c8fe48e77f845d9db0d3c4c4ccf7c4f1;p=qemu.git

target/tricore: Fix OPC1_16_SRO_LD_H translation

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Eitan Eliahu <eitan_eliahu@hotmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/652
Message-Id: <20230112142258.514079-1-anton.kochkov@proton.me>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---

diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index ab386cef50..7ac34efd76 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -3878,7 +3878,7 @@ static void decode_sro_opc(DisasContext *ctx, int op1)
         gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_UB);
         break;
     case OPC1_16_SRO_LD_H:
-        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address, MO_LESW);
+        gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 2, MO_LESW);
         break;
     case OPC1_16_SRO_LD_W:
         gen_offset_ld(ctx, cpu_gpr_d[15], cpu_gpr_a[r2], address * 4, MO_LESL);