From: Oak Zeng Date: Sat, 23 Jan 2021 03:51:39 +0000 (-0600) Subject: drm/amdgpu: Fix GART page table s-bit X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=79194dacb26a1b31c6d3259144c371795612ce75;p=linux.git drm/amdgpu: Fix GART page table s-bit For the new 2-level GART table, the last PDE0 points to PTB. Since PTB is in vram and right now we are runing under s=0 mode (vram is treated as FB carveout), so the s bit of this PDE0 should be set to 0. Signed-off-by: Oak Zeng Reviewed-by: Felix Kuehling Signed-off-by: Alex Deucher --- diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c index 3ab85a445d6ff..ebd22ae76e8f9 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c @@ -656,7 +656,7 @@ void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev) * PTB who has more than 512 entries each * pointing to a 4K system page */ - flags = AMDGPU_PTE_VALID | AMDGPU_PTE_SYSTEM; + flags = AMDGPU_PTE_VALID; flags |= AMDGPU_PDE_BFS(0) | AMDGPU_PTE_SNOOPED; /* Requires gart_ptb_gpu_pa to be 4K aligned */ amdgpu_gmc_set_pte_pde(adev, adev->gmc.ptr_pdb0, i, gart_ptb_gpu_pa, flags);