From: Rebecca Cran Date: Wed, 12 May 2021 18:23:37 +0000 (-0600) Subject: target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=7b9171cc83f37d078ae7d544d2bacd6a851453d8;p=qemu.git target/arm: set ID_AA64ISAR0.TLB to 2 for max AARCH64 CPU type Indicate support for FEAT_TLBIOS and FEAT_TLBIRANGE by setting ID_AA64ISAR0.TLB to 2 for the max AARCH64 CPU type. Signed-off-by: Rebecca Cran Reviewed-by: Richard Henderson Message-id: 20210512182337.18563-4-rebecca@nuviainc.com Signed-off-by: Peter Maydell --- diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f0a9e968c9..f42803ecaf 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -651,6 +651,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ + t = FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ t = FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); cpu->isar.id_aa64isar0 = t;