From: Peter Maydell Date: Tue, 25 Aug 2015 15:24:06 +0000 (+0100) Subject: Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150825-1' into... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=7df9671989c1cfa693764f9ae6349324b2ada02a;p=qemu.git Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20150825-1' into staging target-arm queue: * add missing EL2/EL3 TLBI operations * add missing EL2/EL3 ATS operations * add missing EL2/EL3 registers * update Xilinx MAINTAINERS info * Xilinx: connect the four OCM banks # gpg: Signature made Tue 25 Aug 2015 16:22:43 BST using RSA key ID 14360CDE # gpg: Good signature from "Peter Maydell " # gpg: aka "Peter Maydell " # gpg: aka "Peter Maydell " * remotes/pmaydell/tags/pull-target-arm-20150825-1: target-arm: Implement AArch64 TLBI operations on IPAs target-arm: Implement missing EL3 TLB invalidate operations target-arm: Implement missing EL2 TLBI operations target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order cputlb: Add functions for flushing TLB for a single MMU index target-arm: Implement AArch32 ATS1H* operations target-arm: Enable the AArch32 ATS12NSO ops target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 target-arm: Wire up AArch64 EL2 and EL3 address translation ops target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations target-arm: Implement missing ACTLR registers target-arm: Implement missing AFSR registers target-arm: Implement missing AMAIR registers target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers MAINTAINERS: Add ZynqMP to MAINTAINERS file MAINTAINERS: Update Xilinx Maintainership xlnx-zynqmp: Connect the four OCM banks Signed-off-by: Peter Maydell --- 7df9671989c1cfa693764f9ae6349324b2ada02a