From: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Date: Wed, 13 Jun 2018 08:30:13 +0000 (+0100)
Subject: mos6522: only clear the shift register interrupt upon write
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=7f5d6517e303e39d79f57ca92919725e03c9fad8;p=qemu.git

mos6522: only clear the shift register interrupt upon write

According to the 6522 datasheet the shift register (SR) interrupt flag is
cleared upon write with no mention of any other interrupt flags.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
---

diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c
index 44eb306cf1..ad5041d8c0 100644
--- a/hw/misc/mos6522.c
+++ b/hw/misc/mos6522.c
@@ -241,7 +241,7 @@ uint64_t mos6522_read(void *opaque, hwaddr addr, unsigned size)
         break;
     case VIA_REG_SR:
         val = s->sr;
-        s->ifr &= ~(SR_INT | CB1_INT | CB2_INT);
+        s->ifr &= ~SR_INT;
         mos6522_update_irq(s);
         break;
     case VIA_REG_ACR: