From: Conor Dooley Date: Thu, 8 Sep 2022 14:36:48 +0000 (+0100) Subject: dt-bindings: clk: rename mpfs-clkcfg binding X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=803307a452e787af92789db16a156c35e60f8aaf;p=linux.git dt-bindings: clk: rename mpfs-clkcfg binding The filename for a binding is supposed to match the first compatible, but the mpfs-clkcfg file did not follow this policy. Rename it to match so that when other mpfs clock bindings are added things make more sense. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley Signed-off-by: Claudiu Beznea Link: https://lore.kernel.org/r/20220908143651.1252601-2-conor.dooley@microchip.com --- diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml new file mode 100644 index 0000000000000..b2ce78722247c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs-clkcfg.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs-clkcfg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Clock Control Module Binding + +maintainers: + - Daire McNamara + +description: | + Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, + which gates and enables all peripheral clocks. + + This device tree binding describes 33 gate clocks. Clocks are referenced by + user nodes by the CLKCFG node phandle and the clock index in the group, from + 0 to 32. + +properties: + compatible: + const: microchip,mpfs-clkcfg + + reg: + items: + - description: | + clock config registers: + These registers contain enable, reset & divider tables for the, cpu, + axi, ahb and rtc/mtimer reference clocks as well as enable and reset + for the peripheral clocks. + - description: | + mss pll dri registers: + Block of registers responsible for dynamic reconfiguration of the mss + pll + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + + resets: + maxItems: 1 + + '#reset-cells': + description: + The AHB/AXI peripherals on the PolarFire SoC have reset support, so from + CLK_ENVM to CLK_CFM. The reset consumer should specify the desired + peripheral via the clock ID in its "resets" phandle cell. + See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of + PolarFire clock IDs. + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Config node: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + clkcfg: clock-controller@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; + clocks = <&ref>; + #clock-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml deleted file mode 100644 index 1d0b6a4fda42d..0000000000000 --- a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml +++ /dev/null @@ -1,80 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Microchip PolarFire Clock Control Module Binding - -maintainers: - - Daire McNamara - -description: | - Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, - which gates and enables all peripheral clocks. - - This device tree binding describes 33 gate clocks. Clocks are referenced by - user nodes by the CLKCFG node phandle and the clock index in the group, from - 0 to 32. - -properties: - compatible: - const: microchip,mpfs-clkcfg - - reg: - items: - - description: | - clock config registers: - These registers contain enable, reset & divider tables for the, cpu, - axi, ahb and rtc/mtimer reference clocks as well as enable and reset - for the peripheral clocks. - - description: | - mss pll dri registers: - Block of registers responsible for dynamic reconfiguration of the mss - pll - - clocks: - maxItems: 1 - - '#clock-cells': - const: 1 - description: | - The clock consumer should specify the desired clock by having the clock - ID in its "clocks" phandle cell. - See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of - PolarFire clock IDs. - - resets: - maxItems: 1 - - '#reset-cells': - description: - The AHB/AXI peripherals on the PolarFire SoC have reset support, so from - CLK_ENVM to CLK_CFM. The reset consumer should specify the desired - peripheral via the clock ID in its "resets" phandle cell. - See include/dt-bindings/clock/microchip,mpfs-clock.h for the full list of - PolarFire clock IDs. - const: 1 - -required: - - compatible - - reg - - clocks - - '#clock-cells' - -additionalProperties: false - -examples: - # Clock Config node: - - | - #include - soc { - #address-cells = <2>; - #size-cells = <2>; - clkcfg: clock-controller@20002000 { - compatible = "microchip,mpfs-clkcfg"; - reg = <0x0 0x20002000 0x0 0x1000>, <0x0 0x3E001000 0x0 0x1000>; - clocks = <&ref>; - #clock-cells = <1>; - }; - };