From: Markos Chandras Date: Fri, 18 Jul 2014 09:51:31 +0000 (+0100) Subject: MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=80bc94d10466c710158d5f30c43625ed9fa59e78;p=linux.git MIPS: pgtable-bits: Define the CCA bit for WC writes on Ingenic cores Ingenic uses the CCA:1 bit to achieve write-combine memory writes. Signed-off-by: Markos Chandras Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/7401/ Signed-off-by: Ralf Baechle --- diff --git a/arch/mips/include/asm/pgtable-bits.h b/arch/mips/include/asm/pgtable-bits.h index 011b0dcf306e8..e747bfa0be7e0 100644 --- a/arch/mips/include/asm/pgtable-bits.h +++ b/arch/mips/include/asm/pgtable-bits.h @@ -240,6 +240,11 @@ static inline uint64_t pte_to_entrylo(unsigned long pte_val) #define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT) /* LOONGSON */ #define _CACHE_CACHABLE_COHERENT (3<<_CACHE_SHIFT) /* LOONGSON-3 */ +#elif defined(CONFIG_MACH_JZ4740) + +/* Ingenic uses the WA bit to achieve write-combine memory writes */ +#define _CACHE_UNCACHED_ACCELERATED (1<<_CACHE_SHIFT) + #endif #ifndef _CACHE_CACHABLE_NO_WA