From: Kathiravan Thirumoorthy Date: Thu, 14 Sep 2023 06:59:58 +0000 (+0530) Subject: arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=80ebe63329909531afc87335f1d95c7bf8414438;p=linux.git arm64: dts: qcom: ipq8074: include the GPLL0 as clock provider for mailbox While the kernel is booting up, APSS clock / CPU clock will be running at 800MHz with GPLL0 as source. Once the cpufreq driver is available, APSS PLL will be configured to the rate based on the opp table and the source also will be changed to APSS_PLL_EARLY. So allow the mailbox to consume the GPLL0, with this inclusion, CPU Freq correctly reports that CPU is running at 800MHz rather than 24MHz. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230913-gpll_cleanup-v2-8-c8ceb1a37680@quicinc.com [bjorn: Updated commit message, as requested by Kathiravan] Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 2f275c84e5665..5d05819f356d7 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -708,8 +708,8 @@ compatible = "qcom,ipq8074-apcs-apps-global", "qcom,ipq6018-apcs-apps-global"; reg = <0x0b111000 0x1000>; - clocks = <&a53pll>, <&xo>; - clock-names = "pll", "xo"; + clocks = <&a53pll>, <&xo>, <&gcc GPLL0>; + clock-names = "pll", "xo", "gpll0"; #clock-cells = <1>; #mbox-cells = <1>;