From: Shaik Sajida Bhanu Date: Thu, 10 Jun 2021 07:11:47 +0000 (+0530) Subject: arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=81cfa462e458405f58b23f45ddd9439c70bf5347;p=linux.git arm64: dts: qcom: sc7180: Add xo clock for eMMC and Sd card The calculations for the DLL register values are based on the clock rate of the reference clock. Provide the reference clock in the definition of the two SDHCI controllers to not rely on the default values. Reviewed-by: Konrad Dybcio Signed-off-by: Shaik Sajida Bhanu Link: https://lore.kernel.org/r/1623309107-27833-1-git-send-email-sbhanu@codeaurora.org [bjorn: Rewrote commit message] Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index 52115e0359bdf..fb1d9ad8bf6c8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -701,8 +701,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC1_APPS_CLK>, - <&gcc GCC_SDCC1_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC1_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>; interconnect-names = "sdhc-ddr","cpu-sdhc"; @@ -2564,8 +2565,9 @@ interrupt-names = "hc_irq", "pwr_irq"; clocks = <&gcc GCC_SDCC2_APPS_CLK>, - <&gcc GCC_SDCC2_AHB_CLK>; - clock-names = "core", "iface"; + <&gcc GCC_SDCC2_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "core", "iface", "xo"; interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;