From: Bjorn Helgaas <bhelgaas@google.com>
Date: Thu, 16 May 2024 23:14:09 +0000 (-0500)
Subject: Merge branch 'pci/cxl'
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=83711a1ab210cf59d30a3e65f72268f5404c1870;p=linux.git

Merge branch 'pci/cxl'

- Lock the upstream bridge while using it to perform a Secondary Bus Reset
  (Dave Jiang)

- Return failure when attempting Secondary Bus Reset below a CXL Port that
  has SBR masked (Dave Jiang)

- Add a "cxl_bus" reset method that temporarily unmasks SBR (Dave Jiang)

- Add a warning if we reset a CXL type 3 memory device that was in use
  while being reset (Dave Jiang)

* pci/cxl:
  cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders
  PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports
  PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked
  PCI: Lock upstream bridge for pci_reset_function()
  PCI/CXL: Move CXL Vendor ID to pci_ids.h
---

83711a1ab210cf59d30a3e65f72268f5404c1870