From: Hou Zhiqiang Date: Fri, 11 Mar 2022 23:49:36 +0000 (-0600) Subject: dt-bindings: pci: layerscape-pci: Update the description of SCFG property X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=84f293b204ab1ef519278e7993e9930f03879627;p=linux.git dt-bindings: pci: layerscape-pci: Update the description of SCFG property Update the description of the second entry of 'fsl,pcie-scfg' property, as the LS1043A PCIe controller also has some control registers in SCFG block, while it has 3 controllers. Link: https://lore.kernel.org/r/20220311234938.8706-3-leoyang.li@nxp.com Signed-off-by: Hou Zhiqiang Signed-off-by: Lorenzo Pieralisi Acked-by: Rob Herring --- diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt index 215d2ee65c835..f1115fcd8088d 100644 --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt @@ -34,7 +34,7 @@ Required properties: "intr": The interrupt that is asserted for controller interrupts - fsl,pcie-scfg: Must include two entries. The first entry must be a link to the SCFG device node - The second entry must be '0' or '1' based on physical PCIe controller index. + The second entry is the physical PCIe controller index starting from '0'. This is used to get SCFG PEXN registers - dma-coherent: Indicates that the hardware IP block can ensure the coherency of the data transferred from/to the IP block. This can avoid the software