From: Richard Henderson <richard.henderson@linaro.org>
Date: Fri, 23 Jun 2023 10:15:43 +0000 (+0100)
Subject: target/arm: SCR_EL3.NS may be RES1
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=87bfbfe7e595372251037c28223919659a294fd3;p=qemu.git

target/arm: SCR_EL3.NS may be RES1

With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230620124418.805717-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---

diff --git a/target/arm/helper.c b/target/arm/helper.c
index d2f0d9226e..9132d4de6a 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1855,6 +1855,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
         }
         if (cpu_isar_feature(aa64_sel2, cpu)) {
             valid_mask |= SCR_EEL2;
+        } else if (cpu_isar_feature(aa64_rme, cpu)) {
+            /* With RME and without SEL2, NS is RES1 (R_GSWWH, I_DJJQJ). */
+            value |= SCR_NS;
         }
         if (cpu_isar_feature(aa64_mte, cpu)) {
             valid_mask |= SCR_ATA;