From: Changbin Du Date: Sat, 28 Mar 2020 14:02:32 +0000 (+0800) Subject: target/arm: fix incorrect current EL bug in aarch32 exception emulation X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=88828bf133b64b7a860c166af3423ef1a47c5d3b;p=qemu.git target/arm: fix incorrect current EL bug in aarch32 exception emulation The arm_current_el() should be invoked after mode switching. Otherwise, we get a wrong current EL value, since current EL is also determined by current mode. Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") Signed-off-by: Changbin Du Reviewed-by: Richard Henderson Message-id: 20200328140232.17278-1-changbin.du@gmail.com Signed-off-by: Peter Maydell --- diff --git a/target/arm/helper.c b/target/arm/helper.c index b7b6887241..163c91a1cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); - new_el = arm_current_el(env); /* * For exceptions taken to AArch32 we must clear the SS bit in both @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->condexec_bits = 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el = arm_current_el(env); + /* Set new mode endianness */ env->uncached_cpsr &= ~CPSR_E; if (env->cp15.sctlr_el[new_el] & SCTLR_EE) {