From: Huacai Chen Date: Wed, 28 Oct 2020 04:18:00 +0000 (+0800) Subject: target/mips: Add unaligned access support for MIPS64R6 and Loongson-3 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8a805609d126ff2be9ad9ec118185dfc52633d6f;p=qemu.git target/mips: Add unaligned access support for MIPS64R6 and Loongson-3 MIPSR6 (not only MIPS32R6) processors support unaligned access in hardware, so set MO_UNALN in their default_tcg_memop_mask. Btw, new Loongson-3 (such as Loongson-3A4000) also support unaligned access, since both old and new Loongson-3 use the same binaries, we can simply set MO_UNALN for all Loongson-3 processors. Signed-off-by: Huacai Chen Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Message-Id: <1604053541-27822-3-git-send-email-chenhc@lemote.com> Signed-off-by: Philippe Mathieu-Daudé --- diff --git a/target/mips/translate.c b/target/mips/translate.c index 3197a692c4..c64a1bc42e 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -31442,8 +31442,8 @@ static void mips_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) #else ctx->mem_idx = hflags_mmu_index(ctx->hflags); #endif - ctx->default_tcg_memop_mask = (ctx->insn_flags & ISA_MIPS32R6) ? - MO_UNALN : MO_ALIGN; + ctx->default_tcg_memop_mask = (ctx->insn_flags & (ISA_MIPS32R6 | ISA_MIPS64R6 | + INSN_LOONGSON3A)) ? MO_UNALN : MO_ALIGN; LOG_DISAS("\ntb %p idx %d hflags %04x\n", ctx->base.tb, ctx->mem_idx, ctx->hflags);