From: Sai Krishna Potthuri Date: Mon, 3 Apr 2023 10:25:49 +0000 (+0530) Subject: dt-bindings: mmc: arasan,sdci: Add Xilinx Versal Net compatible X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8aa7206411fce5a2c6e2643df5c91e6d3e583ba8;p=linux.git dt-bindings: mmc: arasan,sdci: Add Xilinx Versal Net compatible Add Xilinx Versal Net compatible to support eMMC 5.1 PHY. Signed-off-by: Sai Krishna Potthuri Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20230403102551.3763054-2-sai.krishna.potthuri@amd.com Signed-off-by: Ulf Hansson --- diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml index e8e8b48dc5e54..a6c19a6cc99e3 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml @@ -27,6 +27,7 @@ allOf: enum: - xlnx,zynqmp-8.9a - xlnx,versal-8.9a + - xlnx,versal-net-emmc then: properties: clock-output-names: @@ -62,6 +63,10 @@ properties: description: For this device it is strongly suggested to include clock-output-names and '#clock-cells'. + - const: xlnx,versal-net-emmc # Versal Net eMMC PHY + description: + For this device it is strongly suggested to include + clock-output-names and '#clock-cells'. - items: - const: intel,lgm-sdhci-5.1-emmc # Intel LGM eMMC PHY - const: arasan,sdhci-5.1