From: Bhavya Kapoor Date: Fri, 1 Dec 2023 08:20:45 +0000 (+0530) Subject: arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8bbe8a7dbaabb84d93321f116966af73ba6a7233;p=linux.git arm64: dts: ti: k3-j784s4-main: Add Itap Delay Value For DDR50 speed mode DDR50 speed mode is enabled for MMCSD in J784s4 but its Itap Delay Value is not present in the device tree. Thus, add Itap Delay Value for MMCSD High Speed DDR which is DDR50 speed mode for J784s4 SoC according to datasheet for J784s4. [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface, in J784s4 datasheet - https://www.ti.com/lit/ds/symlink/tda4vh-q1.pdf Signed-off-by: Bhavya Kapoor Reviewed-by: Judith Mendez Reviewed-by: Udit Kumar Link: https://lore.kernel.org/r/20231201082045.790478-4-b-kapoor@ti.com Signed-off-by: Nishanth Menon --- diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 827328450f96d..f2b720ed1e4f2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -712,6 +712,7 @@ ti,itap-del-sel-sd-hs = <0x0>; ti,itap-del-sel-sdr12 = <0x0>; ti,itap-del-sel-sdr25 = <0x0>; + ti,itap-del-sel-ddr50 = <0x2>; ti,clkbuf-sel = <0x7>; ti,trm-icp = <0x8>; dma-coherent;