From: Mark Brown Date: Fri, 20 May 2022 16:16:36 +0000 (+0100) Subject: arm64/sysreg: Generate definitions for CSSELR_EL1 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8bd354b30533632396627291c4a3792f9c2947b2;p=linux.git arm64/sysreg: Generate definitions for CSSELR_EL1 Convert CSSELR_EL1 to automatic generation as per DDI0487H.a, no functional change. Signed-off-by: Mark Brown Reviewed-by: Mark Rutland Link: https://lore.kernel.org/r/20220520161639.324236-5-broonie@kernel.org Signed-off-by: Catalin Marinas --- diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h index 7603c3344697c..d1ca7f11e1105 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -462,8 +462,6 @@ #define SMIDR_EL1_SMPS_SHIFT 15 #define SMIDR_EL1_AFFINITY_SHIFT 0 -#define SYS_CSSELR_EL1 sys_reg(3, 2, 0, 0, 0) - #define SYS_CTR_EL0 sys_reg(3, 3, 0, 0, 1) #define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index 4bf413770b65c..759075747dcc3 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -262,6 +262,13 @@ Res0 14:12 Field 11:0 AFFINITY EndSysreg +Sysreg CSSELR_EL1 3 2 0 0 0 +Res0 63:5 +Field 4 TnD +Field 3:1 Level +Field 0 InD +EndSysreg + Sysreg SVCR 3 3 4 2 2 Res0 63:2 Field 1 ZA