From: Pierre Gondois Date: Fri, 20 Oct 2023 19:50:22 +0000 (-0500) Subject: arm64: dts: Update cache properties for socionext X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8d4f9145f52e9d1c5e6e86402ef8ca24cadb38f9;p=linux.git arm64: dts: Update cache properties for socionext The DeviceTree Specification v0.3 specifies that the cache node 'compatible' and 'cache-level' properties are 'required'. Cf. s3.8 Multi-level and Shared Cache Nodes The 'cache-unified' property should be present if one of the properties for unified cache is present ('cache-size', ...). Update the Device Trees accordingly. Signed-off-by: Pierre Gondois Reviewed-by: Kunihiko Hayashi Link: https://lore.kernel.org/r/20221107155825.1644604-21-pierre.gondois@arm.com Signed-off-by: Rob Herring Reviewed-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20231020195022.4183862-2-robh@kernel.org Signed-off-by: Arnd Bergmann --- diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi index 7bb36b0714751..54e58d945fd77 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi @@ -52,6 +52,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi index 4e2171630272d..18390cba2eda0 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi @@ -86,10 +86,12 @@ a72_l2: l2-cache0 { compatible = "cache"; + cache-level = <2>; }; a53_l2: l2-cache1 { compatible = "cache"; + cache-level = <2>; }; }; diff --git a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi index 38ccfb46ea425..56e0379008186 100644 --- a/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi +++ b/arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi @@ -83,6 +83,7 @@ l2: l2-cache { compatible = "cache"; + cache-level = <2>; }; };