From: Matthew Auld Date: Wed, 29 Nov 2023 10:37:07 +0000 (+0000) Subject: drm/xe/mocs: update MOCS table for xe2 X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8e35780233cee1b2d257e6adf4d82b08ded15e88;p=linux.git drm/xe/mocs: update MOCS table for xe2 Looks like there were some changes at some point here for preferring L4 uncached for some of the indexes. Triple checked the PAT settings also, but that looks all correct as per current BSpec. BSpec: 71582 Signed-off-by: Matthew Auld Cc: Lucas De Marchi Cc: Matt Roper Reviewed-by: Lucas De Marchi Signed-off-by: Rodrigo Vivi --- diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index 12a6d39fcd4a4..ef79552e4f2fe 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -366,9 +366,9 @@ static const struct xe_mocs_entry mtl_mocs_desc[] = { static const struct xe_mocs_entry xe2_mocs_table[] = { /* Defer to PAT */ - MOCS_ENTRY(0, XE2_L3_0_WB | L4_0_WB, 0), - /* Cached L3 + L4 */ - MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_0_WB, 0), + MOCS_ENTRY(0, XE2_L3_0_WB | L4_3_UC, 0), + /* Cached L3, Uncached L4 */ + MOCS_ENTRY(1, IG_PAT | XE2_L3_0_WB | L4_3_UC, 0), /* Uncached L3, Cached L4 */ MOCS_ENTRY(2, IG_PAT | XE2_L3_3_UC | L4_0_WB, 0), /* Uncached L3 + L4 */ @@ -390,8 +390,8 @@ static unsigned int get_mocs_settings(struct xe_device *xe, info->table = xe2_mocs_table; info->n_entries = XE2_NUM_MOCS_ENTRIES; info->uc_index = 3; - info->wb_index = 1; - info->unused_entries_index = 1; + info->wb_index = 4; + info->unused_entries_index = 4; break; case XE_PVC: info->size = ARRAY_SIZE(pvc_mocs_desc);