From: Palmer Dabbelt <palmer@rivosinc.com>
Date: Thu, 2 Mar 2023 01:28:21 +0000 (-0800)
Subject: Merge patch series "target/riscv: Add support for Svadu extension"
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8e5aded3de88e9403bd95b152e2a5597b5d92895;p=qemu.git

Merge patch series "target/riscv: Add support for Svadu extension"

Weiwei Li <liweiwei@iscas.ac.cn> says:

This patchset adds support svadu extension. It also fixes some
relationship between *envcfg fields and Svpbmt/Sstc extensions.

Specification for Svadu extension can be found in:

https://github.com/riscv/riscv-svadu

* b4-shazam-merge:
  target/riscv: Export Svadu property
  target/riscv: Add *envcfg.HADE related check in address translation
  target/riscv: Add *envcfg.PBMTE related check in address translation
  target/riscv: Add csr support for svadu
  target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg
  target/riscv: Fix the relationship between menvcfg.PBMTE/STCE and Svpbmt/Sstc extensions

Message-ID: <20230224040852.37109-1-liweiwei@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---

8e5aded3de88e9403bd95b152e2a5597b5d92895
diff --cc target/riscv/csr.c
index a2cf3536f0,be71c50f09..ee49b636f5
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@@ -1877,8 -1883,9 +1877,9 @@@ static RISCVException read_menvcfg(CPUR
  }
  
  static RISCVException write_menvcfg(CPURISCVState *env, int csrno,
 -                                  target_ulong val)
 +                                    target_ulong val)
  {
+     RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
      uint64_t mask = MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCFG_CBZE;
  
      if (riscv_cpu_mxl(env) == MXL_RV64) {
@@@ -1897,9 -1906,12 +1900,12 @@@ static RISCVException read_menvcfgh(CPU
  }
  
  static RISCVException write_menvcfgh(CPURISCVState *env, int csrno,
 -                                  target_ulong val)
 +                                     target_ulong val)
  {
-     uint64_t mask = MENVCFG_PBMTE | MENVCFG_STCE;
+     RISCVCPUConfig *cfg = &env_archcpu(env)->cfg;
+     uint64_t mask = (cfg->ext_svpbmt ? MENVCFG_PBMTE : 0) |
+                     (cfg->ext_sstc ? MENVCFG_STCE : 0) |
+                     (cfg->ext_svadu ? MENVCFG_HADE : 0);
      uint64_t valh = (uint64_t)val << 32;
  
      env->menvcfg = (env->menvcfg & ~mask) | (valh & mask);
@@@ -2018,9 -2004,10 +2031,10 @@@ static RISCVException read_henvcfgh(CPU
  }
  
  static RISCVException write_henvcfgh(CPURISCVState *env, int csrno,
 -                                  target_ulong val)
 +                                     target_ulong val)
  {
-     uint64_t mask = HENVCFG_PBMTE | HENVCFG_STCE;
+     uint64_t mask = env->menvcfg & (HENVCFG_PBMTE | HENVCFG_STCE |
+                                     HENVCFG_HADE);
      uint64_t valh = (uint64_t)val << 32;
      RISCVException ret;