From: Sibi Sankar <sibis@codeaurora.org>
Date: Tue, 24 Nov 2020 06:21:15 +0000 (+0530)
Subject: arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=8fd01e01fd6f;p=linux.git

arm64: dts: qcom: sc7180-lite: Tweak DDR/L3 scaling on SC7180-lite

Tweak the DDR/L3 bandwidth votes on the lite variant of the SC7180 SoC
since the gold cores only support frequencies upto 2.1 GHz.

Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Link: https://lore.kernel.org/r/1606198876-3515-1-git-send-email-sibis@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
new file mode 100644
index 0000000000000..d8ed1d7b4ec76
--- /dev/null
+++ b/arch/arm64/boot/dts/qcom/sc7180-lite.dtsi
@@ -0,0 +1,18 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * SC7180 lite device tree source
+ *
+ * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ */
+
+&cpu6_opp10 {
+	opp-peak-kBps = <7216000 22425600>;
+};
+
+&cpu6_opp11 {
+	opp-peak-kBps = <7216000 22425600>;
+};
+
+&cpu6_opp12 {
+	opp-peak-kBps = <8532000 23347200>;
+};