From: Aurelien Jarno <aurelien@aurel32.net>
Date: Fri, 9 Apr 2010 18:52:48 +0000 (+0200)
Subject: tcg/arm: optimize register allocation order
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=914ccf51b07af860021863e0f8e46eac9ffbcb68;p=qemu.git

tcg/arm: optimize register allocation order

The beginning of the register allocation order list on the TCG arm
target matches the list of clobbered registers. This means that when an
helper is called, there is almost always clobbered registers that have
to be spilled.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---

diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index a60637e54d..c07d28415e 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -89,10 +89,6 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
 #endif
 
 static const int tcg_target_reg_alloc_order[] = {
-    TCG_REG_R0,
-    TCG_REG_R1,
-    TCG_REG_R2,
-    TCG_REG_R3,
     TCG_REG_R4,
     TCG_REG_R5,
     TCG_REG_R6,
@@ -101,8 +97,12 @@ static const int tcg_target_reg_alloc_order[] = {
     TCG_REG_R9,
     TCG_REG_R10,
     TCG_REG_R11,
-    TCG_REG_R12,
     TCG_REG_R13,
+    TCG_REG_R0,
+    TCG_REG_R1,
+    TCG_REG_R2,
+    TCG_REG_R3,
+    TCG_REG_R12,
     TCG_REG_R14,
 };