From: Rob Herring Date: Fri, 3 Jun 2022 01:19:31 +0000 (-0500) Subject: dt-bindings: arm: Rename Coresight filenames to match compatible X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=92c2b1c12f8a908d849b64717e8809981b66f759;p=linux.git dt-bindings: arm: Rename Coresight filenames to match compatible Use the compatible strings for filenames as that is the preferred naming convention for DT bindings. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20220603011933.3277315-2-robh@kernel.org Signed-off-by: Mathieu Poirier --- diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml new file mode 100644 index 0000000000000..d32d214ed64ec --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml @@ -0,0 +1,332 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2019 Linaro Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ARM Coresight Cross Trigger Interface (CTI) device. + +description: | + The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected + to one or more CoreSight components and/or a CPU, with CTIs interconnected in + a star topology via the Cross Trigger Matrix (CTM), which is not programmable. + The ECT components are not part of the trace generation data path and are thus + not part of the CoreSight graph described in the general CoreSight bindings + file coresight.txt. + + The CTI component properties define the connections between the individual + CTI and the components it is directly connected to, consisting of input and + output hardware trigger signals. CTIs can have a maximum number of input and + output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The + number is defined at design time, the maximum of each defined in the DEVID + register. + + CTIs are interconnected in a star topology via the CTM, using a number of + programmable channels, usually 4, but again implementation defined and + described in the DEVID register. The star topology is not required to be + described in the bindings as the actual connections are software + programmable. + + In general the connections between CTI and components via the trigger signals + are implementation defined, except when the CTI is connected to an ARM v8 + architecture core and optional ETM. + + In this case the ARM v8 architecture defines the required signal connections + between CTI and the CPU core and ETM if present. In the case of a v8 + architecturally connected CTI an additional compatible string is used to + indicate this feature (arm,coresight-cti-v8-arch). + + When CTI trigger connection information is unavailable then a minimal driver + binding can be declared with no explicit trigger signals. This will result + the driver detecting the maximum available triggers and channels from the + DEVID register and make them all available for use as a single default + connection. Any user / client application will require additional information + on the connections between the CTI and other components for correct operation. + This information might be found by enabling the Integration Test registers in + the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel + configuration). These registers may be used to explore the trigger connections + between CTI and other CoreSight components. + + Certain triggers between CoreSight devices and the CTI have specific types + and usages. These can be defined along with the signal indexes with the + constants defined in + + For example a CTI connected to a core will usually have a DBGREQ signal. This + is defined in the binding as type PE_EDBGREQ. These types will appear in an + optional array alongside the signal indexes. Omitting types will default all + signals to GEN_IO. + + Note that some hardware trigger signals can be connected to non-CoreSight + components (e.g. UART etc) depending on hardware implementation. + +maintainers: + - Mike Leach + +allOf: + - $ref: /schemas/arm/primecell.yaml# + +# Need a custom select here or 'arm,primecell' will match on lots of nodes +select: + properties: + compatible: + contains: + enum: + - arm,coresight-cti + required: + - compatible + +properties: + $nodename: + pattern: "^cti(@[0-9a-f]+)$" + compatible: + oneOf: + - items: + - const: arm,coresight-cti + - const: arm,primecell + - items: + - const: arm,coresight-cti-v8-arch + - const: arm,coresight-cti + - const: arm,primecell + + reg: + maxItems: 1 + + cpu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Handle to cpu this device is associated with. This must appear in the + base cti node if compatible string arm,coresight-cti-v8-arch is used, + or may appear in a trig-conns child node when appropriate. + + arm,cti-ctm-id: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Defines the CTM this CTI is connected to, in large systems with multiple + separate CTI/CTM nets. Typically multi-socket systems where the CTM is + propagated between sockets. + + arm,cs-dev-assoc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + defines a phandle reference to an associated CoreSight trace device. + When the associated trace device is enabled, then the respective CTI + will be enabled. Use in a trig-conns node, or in CTI base node when + compatible string arm,coresight-cti-v8-arch used. If the associated + device has not been registered then the node name will be stored as + the connection name for later resolution. If the associated device is + not a CoreSight device or not registered then the node name will remain + the connection name and automatic enabling will not occur. + + # size cells and address cells required if trig-conns node present. + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + +patternProperties: + '^trig-conns@([0-9]+)$': + type: object + description: + A trigger connections child node which describes the trigger signals + between this CTI and another hardware device. This device may be a CPU, + CoreSight device, any other hardware device or simple external IO lines. + The connection may have both input and output triggers, or only one or the + other. + + properties: + reg: + maxItems: 1 + + arm,trig-in-sigs: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger in signal numbers in use by a trig-conns node. + + arm,trig-in-types: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger in + signals. Types in this array match to the corresponding signal in the + arm,trig-in-sigs array. If the -types array is smaller, or omitted + completely, then the types will default to GEN_IO. + + arm,trig-out-sigs: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signal numbers in use by a trig-conns node. + + arm,trig-out-types: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of constants representing the types for the CTI trigger out + signals. Types in this array match to the corresponding signal + in the arm,trig-out-sigs array. If the "-types" array is smaller, + or omitted completely, then the types will default to GEN_IO. + + arm,trig-filters: + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 32 + description: + List of CTI trigger out signals that will be blocked from becoming + active, unless filtering is disabled on the driver. + + arm,trig-conn-name: + $ref: /schemas/types.yaml#/definitions/string + description: + Defines a connection name that will be displayed, if the cpu or + arm,cs-dev-assoc properties are not being used in this connection. + Principle use for CTI that are connected to non-CoreSight devices, or + external IO. + + anyOf: + - required: + - arm,trig-in-sigs + - required: + - arm,trig-out-sigs + oneOf: + - required: + - arm,trig-conn-name + - required: + - cpu + - required: + - arm,cs-dev-assoc + required: + - reg + +required: + - compatible + - reg + - clocks + - clock-names + +if: + properties: + compatible: + contains: + const: arm,coresight-cti-v8-arch + +then: + required: + - cpu + +unevaluatedProperties: false + +examples: + # minimum CTI definition. DEVID register used to set number of triggers. + - | + cti@20020000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20020000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + }; + # v8 architecturally defined CTI - CPU + ETM connections generated by the + # driver according to the v8 architecture specification. + - | + cti@859000 { + compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", + "arm,primecell"; + reg = <0x859000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + cpu = <&CPU1>; + arm,cs-dev-assoc = <&etm1>; + }; + # Implementation defined CTI - CPU + ETM connections explicitly defined.. + # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h + # #size-cells and #address-cells are required if trig-conns@ nodes present. + - | + #include + + cti@858000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x858000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + arm,cti-ctm-id = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs = <4 5 6 7>; + arm,trig-in-types = ; + arm,trig-out-sigs = <4 5 6 7>; + arm,trig-out-types = ; + arm,cs-dev-assoc = <&etm0>; + }; + + trig-conns@1 { + reg = <1>; + cpu = <&CPU0>; + arm,trig-in-sigs = <0 1>; + arm,trig-in-types = ; + arm,trig-out-sigs=<0 1 2 >; + arm,trig-out-types = ; + + arm,trig-filters = <0>; + }; + }; + # Implementation defined CTI - non CoreSight component connections. + - | + cti@20110000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x20110000 0x1000>; + + clocks = <&soc_smc50mhz>; + clock-names = "apb_pclk"; + + #address-cells = <1>; + #size-cells = <0>; + + trig-conns@0 { + reg = <0>; + arm,trig-in-sigs=<0>; + arm,trig-in-types=; + arm,trig-out-sigs=<0>; + arm,trig-out-types=; + arm,trig-conn-name = "sys_profiler"; + }; + + trig-conns@1 { + reg = <1>; + arm,trig-out-sigs=<2 3>; + arm,trig-out-types=; + arm,trig-conn-name = "watchdog"; + }; + + trig-conns@2 { + reg = <2>; + arm,trig-in-sigs=<1 6>; + arm,trig-in-types=; + arm,trig-conn-name = "g_counter"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml new file mode 100644 index 0000000000000..2415beeb12eae --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml @@ -0,0 +1,75 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Embedded Trace Extensions + +maintainers: + - Suzuki K Poulose + - Mathieu Poirier + +description: | + Arm Embedded Trace Extension(ETE) is a per CPU trace component that + allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 + architecture and has extended support for future architecture changes. + The trace generated by the ETE could be stored via legacy CoreSight + components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer + Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to + legacy CoreSight components, a node must be listed per instance, along + with any optional connection graph as per the coresight bindings. + See bindings/arm/coresight.txt. + +properties: + $nodename: + pattern: "^ete([0-9a-f]+)$" + compatible: + items: + - const: arm,embedded-trace-extension + + cpu: + description: | + Handle to the cpu this ETE is bound to. + $ref: /schemas/types.yaml#/definitions/phandle + + out-ports: + description: | + Output connections from the ETE to legacy CoreSight trace bus. + $ref: /schemas/graph.yaml#/properties/ports + properties: + port: + description: Output connection from the ETE to legacy CoreSight Trace bus. + $ref: /schemas/graph.yaml#/properties/port + +required: + - compatible + - cpu + +additionalProperties: false + +examples: + +# An ETE node without legacy CoreSight connections + - | + ete0 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_0>; + }; +# An ETE node with legacy CoreSight connections + - | + ete1 { + compatible = "arm,embedded-trace-extension"; + cpu = <&cpu_1>; + + out-ports { /* legacy coresight connection */ + port { + ete1_out_port: endpoint { + remote-endpoint = <&funnel_in_port0>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml new file mode 100644 index 0000000000000..b1322658063a4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause +# Copyright 2021, Arm Ltd +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: ARM Trace Buffer Extensions + +maintainers: + - Anshuman Khandual + +description: | + Arm Trace Buffer Extension (TRBE) is a per CPU component + for storing trace generated on the CPU to memory. It is + accessed via CPU system registers. The software can verify + if it is permitted to use the component by checking the + TRBIDR register. + +properties: + $nodename: + const: "trbe" + compatible: + items: + - const: arm,trace-buffer-extension + + interrupts: + description: | + Exactly 1 PPI must be listed. For heterogeneous systems where + TRBE is only supported on a subset of the CPUs, please consult + the arm,gic-v3 binding for details on describing a PPI partition. + maxItems: 1 + +required: + - compatible + - interrupts + +additionalProperties: false + +examples: + + - | + #include + + trbe { + compatible = "arm,trace-buffer-extension"; + interrupts = ; + }; +... diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/coresight-cti.yaml deleted file mode 100644 index 21e3515491f48..0000000000000 --- a/Documentation/devicetree/bindings/arm/coresight-cti.yaml +++ /dev/null @@ -1,332 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -# Copyright 2019 Linaro Ltd. -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/arm/coresight-cti.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: ARM Coresight Cross Trigger Interface (CTI) device. - -description: | - The CoreSight Embedded Cross Trigger (ECT) consists of CTI devices connected - to one or more CoreSight components and/or a CPU, with CTIs interconnected in - a star topology via the Cross Trigger Matrix (CTM), which is not programmable. - The ECT components are not part of the trace generation data path and are thus - not part of the CoreSight graph described in the general CoreSight bindings - file coresight.txt. - - The CTI component properties define the connections between the individual - CTI and the components it is directly connected to, consisting of input and - output hardware trigger signals. CTIs can have a maximum number of input and - output hardware trigger signals (8 each for v1 CTI, 32 each for v2 CTI). The - number is defined at design time, the maximum of each defined in the DEVID - register. - - CTIs are interconnected in a star topology via the CTM, using a number of - programmable channels, usually 4, but again implementation defined and - described in the DEVID register. The star topology is not required to be - described in the bindings as the actual connections are software - programmable. - - In general the connections between CTI and components via the trigger signals - are implementation defined, except when the CTI is connected to an ARM v8 - architecture core and optional ETM. - - In this case the ARM v8 architecture defines the required signal connections - between CTI and the CPU core and ETM if present. In the case of a v8 - architecturally connected CTI an additional compatible string is used to - indicate this feature (arm,coresight-cti-v8-arch). - - When CTI trigger connection information is unavailable then a minimal driver - binding can be declared with no explicit trigger signals. This will result - the driver detecting the maximum available triggers and channels from the - DEVID register and make them all available for use as a single default - connection. Any user / client application will require additional information - on the connections between the CTI and other components for correct operation. - This information might be found by enabling the Integration Test registers in - the driver (set CONFIG_CORESIGHT_CTI_INTEGRATION_TEST in Kernel - configuration). These registers may be used to explore the trigger connections - between CTI and other CoreSight components. - - Certain triggers between CoreSight devices and the CTI have specific types - and usages. These can be defined along with the signal indexes with the - constants defined in - - For example a CTI connected to a core will usually have a DBGREQ signal. This - is defined in the binding as type PE_EDBGREQ. These types will appear in an - optional array alongside the signal indexes. Omitting types will default all - signals to GEN_IO. - - Note that some hardware trigger signals can be connected to non-CoreSight - components (e.g. UART etc) depending on hardware implementation. - -maintainers: - - Mike Leach - -allOf: - - $ref: /schemas/arm/primecell.yaml# - -# Need a custom select here or 'arm,primecell' will match on lots of nodes -select: - properties: - compatible: - contains: - enum: - - arm,coresight-cti - required: - - compatible - -properties: - $nodename: - pattern: "^cti(@[0-9a-f]+)$" - compatible: - oneOf: - - items: - - const: arm,coresight-cti - - const: arm,primecell - - items: - - const: arm,coresight-cti-v8-arch - - const: arm,coresight-cti - - const: arm,primecell - - reg: - maxItems: 1 - - cpu: - $ref: /schemas/types.yaml#/definitions/phandle - description: - Handle to cpu this device is associated with. This must appear in the - base cti node if compatible string arm,coresight-cti-v8-arch is used, - or may appear in a trig-conns child node when appropriate. - - arm,cti-ctm-id: - $ref: /schemas/types.yaml#/definitions/uint32 - description: - Defines the CTM this CTI is connected to, in large systems with multiple - separate CTI/CTM nets. Typically multi-socket systems where the CTM is - propagated between sockets. - - arm,cs-dev-assoc: - $ref: /schemas/types.yaml#/definitions/phandle - description: - defines a phandle reference to an associated CoreSight trace device. - When the associated trace device is enabled, then the respective CTI - will be enabled. Use in a trig-conns node, or in CTI base node when - compatible string arm,coresight-cti-v8-arch used. If the associated - device has not been registered then the node name will be stored as - the connection name for later resolution. If the associated device is - not a CoreSight device or not registered then the node name will remain - the connection name and automatic enabling will not occur. - - # size cells and address cells required if trig-conns node present. - "#size-cells": - const: 0 - - "#address-cells": - const: 1 - -patternProperties: - '^trig-conns@([0-9]+)$': - type: object - description: - A trigger connections child node which describes the trigger signals - between this CTI and another hardware device. This device may be a CPU, - CoreSight device, any other hardware device or simple external IO lines. - The connection may have both input and output triggers, or only one or the - other. - - properties: - reg: - maxItems: 1 - - arm,trig-in-sigs: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 32 - description: - List of CTI trigger in signal numbers in use by a trig-conns node. - - arm,trig-in-types: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 32 - description: - List of constants representing the types for the CTI trigger in - signals. Types in this array match to the corresponding signal in the - arm,trig-in-sigs array. If the -types array is smaller, or omitted - completely, then the types will default to GEN_IO. - - arm,trig-out-sigs: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 32 - description: - List of CTI trigger out signal numbers in use by a trig-conns node. - - arm,trig-out-types: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 32 - description: - List of constants representing the types for the CTI trigger out - signals. Types in this array match to the corresponding signal - in the arm,trig-out-sigs array. If the "-types" array is smaller, - or omitted completely, then the types will default to GEN_IO. - - arm,trig-filters: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 32 - description: - List of CTI trigger out signals that will be blocked from becoming - active, unless filtering is disabled on the driver. - - arm,trig-conn-name: - $ref: /schemas/types.yaml#/definitions/string - description: - Defines a connection name that will be displayed, if the cpu or - arm,cs-dev-assoc properties are not being used in this connection. - Principle use for CTI that are connected to non-CoreSight devices, or - external IO. - - anyOf: - - required: - - arm,trig-in-sigs - - required: - - arm,trig-out-sigs - oneOf: - - required: - - arm,trig-conn-name - - required: - - cpu - - required: - - arm,cs-dev-assoc - required: - - reg - -required: - - compatible - - reg - - clocks - - clock-names - -if: - properties: - compatible: - contains: - const: arm,coresight-cti-v8-arch - -then: - required: - - cpu - -unevaluatedProperties: false - -examples: - # minimum CTI definition. DEVID register used to set number of triggers. - - | - cti@20020000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x20020000 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - }; - # v8 architecturally defined CTI - CPU + ETM connections generated by the - # driver according to the v8 architecture specification. - - | - cti@859000 { - compatible = "arm,coresight-cti-v8-arch", "arm,coresight-cti", - "arm,primecell"; - reg = <0x859000 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - - cpu = <&CPU1>; - arm,cs-dev-assoc = <&etm1>; - }; - # Implementation defined CTI - CPU + ETM connections explicitly defined.. - # Shows use of type constants from dt-bindings/arm/coresight-cti-dt.h - # #size-cells and #address-cells are required if trig-conns@ nodes present. - - | - #include - - cti@858000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x858000 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - - arm,cti-ctm-id = <1>; - - #address-cells = <1>; - #size-cells = <0>; - - trig-conns@0 { - reg = <0>; - arm,trig-in-sigs = <4 5 6 7>; - arm,trig-in-types = ; - arm,trig-out-sigs = <4 5 6 7>; - arm,trig-out-types = ; - arm,cs-dev-assoc = <&etm0>; - }; - - trig-conns@1 { - reg = <1>; - cpu = <&CPU0>; - arm,trig-in-sigs = <0 1>; - arm,trig-in-types = ; - arm,trig-out-sigs=<0 1 2 >; - arm,trig-out-types = ; - - arm,trig-filters = <0>; - }; - }; - # Implementation defined CTI - non CoreSight component connections. - - | - cti@20110000 { - compatible = "arm,coresight-cti", "arm,primecell"; - reg = <0x20110000 0x1000>; - - clocks = <&soc_smc50mhz>; - clock-names = "apb_pclk"; - - #address-cells = <1>; - #size-cells = <0>; - - trig-conns@0 { - reg = <0>; - arm,trig-in-sigs=<0>; - arm,trig-in-types=; - arm,trig-out-sigs=<0>; - arm,trig-out-types=; - arm,trig-conn-name = "sys_profiler"; - }; - - trig-conns@1 { - reg = <1>; - arm,trig-out-sigs=<2 3>; - arm,trig-out-types=; - arm,trig-conn-name = "watchdog"; - }; - - trig-conns@2 { - reg = <2>; - arm,trig-in-sigs=<1 6>; - arm,trig-in-types=; - arm,trig-conn-name = "g_counter"; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/ete.yaml deleted file mode 100644 index 7f9b2d1e11475..0000000000000 --- a/Documentation/devicetree/bindings/arm/ete.yaml +++ /dev/null @@ -1,75 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -# Copyright 2021, Arm Ltd -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/arm/ete.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: ARM Embedded Trace Extensions - -maintainers: - - Suzuki K Poulose - - Mathieu Poirier - -description: | - Arm Embedded Trace Extension(ETE) is a per CPU trace component that - allows tracing the CPU execution. It overlaps with the CoreSight ETMv4 - architecture and has extended support for future architecture changes. - The trace generated by the ETE could be stored via legacy CoreSight - components (e.g, TMC-ETR) or other means (e.g, using a per CPU buffer - Arm Trace Buffer Extension (TRBE)). Since the ETE can be connected to - legacy CoreSight components, a node must be listed per instance, along - with any optional connection graph as per the coresight bindings. - See bindings/arm/coresight.txt. - -properties: - $nodename: - pattern: "^ete([0-9a-f]+)$" - compatible: - items: - - const: arm,embedded-trace-extension - - cpu: - description: | - Handle to the cpu this ETE is bound to. - $ref: /schemas/types.yaml#/definitions/phandle - - out-ports: - description: | - Output connections from the ETE to legacy CoreSight trace bus. - $ref: /schemas/graph.yaml#/properties/ports - properties: - port: - description: Output connection from the ETE to legacy CoreSight Trace bus. - $ref: /schemas/graph.yaml#/properties/port - -required: - - compatible - - cpu - -additionalProperties: false - -examples: - -# An ETE node without legacy CoreSight connections - - | - ete0 { - compatible = "arm,embedded-trace-extension"; - cpu = <&cpu_0>; - }; -# An ETE node with legacy CoreSight connections - - | - ete1 { - compatible = "arm,embedded-trace-extension"; - cpu = <&cpu_1>; - - out-ports { /* legacy coresight connection */ - port { - ete1_out_port: endpoint { - remote-endpoint = <&funnel_in_port0>; - }; - }; - }; - }; - -... diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/trbe.yaml deleted file mode 100644 index 4402d7bfd1fc0..0000000000000 --- a/Documentation/devicetree/bindings/arm/trbe.yaml +++ /dev/null @@ -1,49 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause -# Copyright 2021, Arm Ltd -%YAML 1.2 ---- -$id: "http://devicetree.org/schemas/arm/trbe.yaml#" -$schema: "http://devicetree.org/meta-schemas/core.yaml#" - -title: ARM Trace Buffer Extensions - -maintainers: - - Anshuman Khandual - -description: | - Arm Trace Buffer Extension (TRBE) is a per CPU component - for storing trace generated on the CPU to memory. It is - accessed via CPU system registers. The software can verify - if it is permitted to use the component by checking the - TRBIDR register. - -properties: - $nodename: - const: "trbe" - compatible: - items: - - const: arm,trace-buffer-extension - - interrupts: - description: | - Exactly 1 PPI must be listed. For heterogeneous systems where - TRBE is only supported on a subset of the CPUs, please consult - the arm,gic-v3 binding for details on describing a PPI partition. - maxItems: 1 - -required: - - compatible - - interrupts - -additionalProperties: false - -examples: - - - | - #include - - trbe { - compatible = "arm,trace-buffer-extension"; - interrupts = ; - }; -... diff --git a/MAINTAINERS b/MAINTAINERS index 3cf9842d9233c..6b38f6175b424 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1982,10 +1982,10 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git F: Documentation/ABI/testing/sysfs-bus-coresight-devices-* F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt -F: Documentation/devicetree/bindings/arm/coresight-cti.yaml +F: Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml F: Documentation/devicetree/bindings/arm/coresight.txt -F: Documentation/devicetree/bindings/arm/ete.yaml -F: Documentation/devicetree/bindings/arm/trbe.yaml +F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml +F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml F: Documentation/trace/coresight/* F: drivers/hwtracing/coresight/* F: include/dt-bindings/arm/coresight-cti-dt.h