From: Thierry Reding <treding@nvidia.com>
Date: Mon, 26 Jun 2017 15:37:09 +0000 (+0200)
Subject: arm64: tegra: Add MISC registers on Tegra186
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=94e25dc3a2b55eb9732f6da41bd25b9dccd60b5a;p=linux.git

arm64: tegra: Add MISC registers on Tegra186

The MISC register block found on Tegra186 SoCs contains registers that
can be used to identify a given chip and various strapping options.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 46d1f287fb0fe..11795dbd30f07 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -13,6 +13,12 @@
 	#address-cells = <2>;
 	#size-cells = <2>;
 
+	misc@100000 {
+		compatible = "nvidia,tegra186-misc";
+		reg = <0x0 0x00100000 0x0 0xf000>,
+		      <0x0 0x0010f000 0x0 0x1000>;
+	};
+
 	gpio: gpio@2200000 {
 		compatible = "nvidia,tegra186-gpio";
 		reg-names = "security", "gpio";