From: Alistair Francis <alistair.francis@wdc.com>
Date: Fri, 11 May 2018 17:24:00 +0000 (-0700)
Subject: hw/riscv/sifive_u: Set the interrupt controller number of interrupts
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=98ceee7fdc04526b7c264823a14ef5977b90040a;p=qemu.git

hw/riscv/sifive_u: Set the interrupt controller number of interrupts

Set the interrupt-controller ndev to the correct number taken from the
HiFive Unleashed board.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
---

diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index d3db8ab9f5..4d3ba4e624 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -187,7 +187,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         0x0, memmap[SIFIVE_U_PLIC].size);
     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
     qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7);
-    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 4);
+    qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
     qemu_fdt_setprop_cells(fdt, nodename, "phandle", 2);
     qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", 2);
     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);