From: Arnd Bergmann Date: Mon, 20 Dec 2021 14:55:51 +0000 (+0100) Subject: Merge tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=990102a792c8155a91654cadabcaf7c072dec672;p=linux.git Merge tag 'ti-k3-dt-for-v5.17' of git://git./linux/kernel/git/ti/linux into arm/dt Devicetree changes for TI K3 platforms for v5.17 merge window: * New Platforms: - J721s2 SoC, SoM and Common Processor Board support * New features: - CAN support on AM64 EVM and SK - TimeSync Router on AM64 * Fixes: - Correct d-cache-sets info on J7200 - Fix L2 cache-sets value for J721e/J7200/AM64 - Fixes for dtbs_check warnings wrt serdes_ln_ctrl node on J721e/J7200 - Disable McASP on IoT2050 board to fix dtbs_check warnings * tag 'ti-k3-dt-for-v5.17' of git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux: arch: arm64: ti: Add support J721S2 Common Processor Board arm64: dts: ti: Add initial support for J721S2 System on Module arm64: dts: ti: Add initial support for J721S2 SoC dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721S2 dt-bindings: arm: ti: Add bindings for J721s2 SoC arm64: dts: ti: iot2050: Disable mcasp nodes at dtsi level arm64: dts: ti: k3-am642-evm/sk: Add support for main domain mcan nodes in EVM and disable them on SK arm64: dts: ti: k3-am64-main: Add support for MCAN arm64: dts: ti: k3-j721e-common-proc-board: Add support for mcu and main mcan nodes arm64: dts: ti: k3-j721e: Add support for MCAN nodes arm64: dts: ti: am654-base-board/am65-iot2050-common: Disable mcan nodes arm64: dts: ti: k3-am65-mcu: Add Support for MCAN arm64: dts: ti: k3-am64-main: add timesync router node arm64: dts: ti: k3-j7200: Correct the d-cache-sets info arm64: dts: ti: k3-j721e: Fix the L2 cache sets arm64: dts: ti: k3-j7200: Fix the L2 cache sets arm64: dts: ti: k3-am642: Fix the L2 cache sets arm64: dts: ti: j721e-main: Fix 'dtbs_check' in serdes_ln_ctrl node arm64: dts: ti: j7200-main: Fix 'dtbs_check' serdes_ln_ctrl node arm64: dts: ti: k3-j721e: correct cache-sets info Link: https://lore.kernel.org/r/20211217172806.10023-2-vigneshr@ti.com Signed-off-by: Arnd Bergmann --- 990102a792c8155a91654cadabcaf7c072dec672