From: Matt Roper Date: Fri, 10 Jun 2022 23:08:01 +0000 (-0700) Subject: drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT() X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=9affc1b87ecba31458567359b5a28b0b08920a24;p=linux.git drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT() If we're treating each bit in the EU fuse register as a single EU instead of a pair of EUs, then that also cuts the number of potential EUs per subslice in half. Fixes: 5ac342ef84d7 ("drm/i915/pvc: Add SSEU changes") Signed-off-by: Matt Roper Reviewed-by: Anusha Srivatsa Link: https://patchwork.freedesktop.org/patch/msgid/20220610230801.459577-1-matthew.d.roper@intel.com --- diff --git a/drivers/gpu/drm/i915/gt/intel_sseu.c b/drivers/gpu/drm/i915/gt/intel_sseu.c index 7ef75f0d9c9e0..c6d3050604c89 100644 --- a/drivers/gpu/drm/i915/gt/intel_sseu.c +++ b/drivers/gpu/drm/i915/gt/intel_sseu.c @@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt) */ intel_sseu_set_info(sseu, 1, 32 * max(num_geometry_regs, num_compute_regs), - 16); + HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16); sseu->has_xehp_dss = 1; xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,