From: Chris Rauer Date: Mon, 3 Apr 2023 15:12:30 +0000 (+0100) Subject: hw/ssi: Fix Linux driver init issue with xilinx_spi X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=a0eaa126af3c5a43937a22c58cfb9bb36e4a5001;p=qemu.git hw/ssi: Fix Linux driver init issue with xilinx_spi The problem is that the Linux driver expects the master transaction inhibit bit(R_SPICR_MTI) to be set during driver initialization so that it can detect the fifo size but QEMU defaults it to zero out of reset. The datasheet indicates this bit is active on reset. See page 25, SPI Control Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer Message-id: 20230323182811.2641044-1-crauer@google.com Reviewed-by: Edgar E. Iglesias Signed-off-by: Peter Maydell --- diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 552927622f..d4de2e7aab 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s) txfifo_reset(s); s->regs[R_SPISSR] = ~0; + s->regs[R_SPICR] = R_SPICR_MTI; xlx_spi_update_irq(s); xlx_spi_update_cs(s); }