From: Michael Walle Date: Fri, 18 Mar 2022 20:13:22 +0000 (+0100) Subject: dt-bindings: net: mscc-miim: add lan966x compatible X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=a2e4b5adfdf85d4a94af8a7a9f44e3ee254fd77e;p=linux.git dt-bindings: net: mscc-miim: add lan966x compatible The MDIO controller has support to release the internal PHYs from reset by specifying a second memory resource. This is different between the currently supported SparX-5 and the LAN966x. Add a new compatible to distinguish between these two. Signed-off-by: Michael Walle Acked-by: Horatiu Vultur Signed-off-by: Jakub Kicinski --- diff --git a/Documentation/devicetree/bindings/net/mscc-miim.txt b/Documentation/devicetree/bindings/net/mscc-miim.txt index 7104679cf59d5..70e0cb1ee4853 100644 --- a/Documentation/devicetree/bindings/net/mscc-miim.txt +++ b/Documentation/devicetree/bindings/net/mscc-miim.txt @@ -2,7 +2,7 @@ Microsemi MII Management Controller (MIIM) / MDIO ================================================= Properties: -- compatible: must be "mscc,ocelot-miim" +- compatible: must be "mscc,ocelot-miim" or "microchip,lan966x-miim" - reg: The base address of the MDIO bus controller register bank. Optionally, a second register bank can be defined if there is an associated reset register for internal PHYs