From: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Date: Tue, 22 Sep 2020 01:24:44 +0000 (+0800)
Subject: MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=a5ce852398a4efc9df4869a71ff45b9dda58882d;p=linux.git

MIPS: Ingenic: Fix bugs when detecting L2 cache of JZ4775 and X1000E.

1.Fix bugs when detecting ways value of JZ4775's L2 cache.
2.Fix bugs when detecting sets value and ways value of X1000E's L2 cache.

Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
---

diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c
index 97dc0511e63f9..dd0a5becaabd8 100644
--- a/arch/mips/mm/sc-mips.c
+++ b/arch/mips/mm/sc-mips.c
@@ -228,6 +228,7 @@ static inline int __init mips_sc_probe(void)
 		 * contradicted by all documentation.
 		 */
 		case MACH_INGENIC_JZ4770:
+		case MACH_INGENIC_JZ4775:
 			c->scache.ways = 4;
 			break;
 
@@ -236,6 +237,7 @@ static inline int __init mips_sc_probe(void)
 		 * but that is contradicted by all documentation.
 		 */
 		case MACH_INGENIC_X1000:
+		case MACH_INGENIC_X1000E:
 			c->scache.sets = 256;
 			c->scache.ways = 4;
 			break;