From: Olof Johansson Date: Sun, 28 Apr 2019 19:59:22 +0000 (-0700) Subject: Merge tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthi... X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=ad88400145a23e063615226f5c69e74945fe17ea;p=linux.git Merge tag 'v5.1-next-dts64' of https://git./linux/kernel/git/matthias.bgg/linux into arm/dt mt8173: - use assinged-clocks and assigned-clock-parents - fix compatible for SoC to a72 - add pmu nodes mt8183: - add sysirq binding - add pinctrl dt header file mt7629: - update bindings description fo sysirq, uart and scpsys mt8516: - add binding description for watchdog, timer, uart and sysirq * tag 'v5.1-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt8173: add pmu nodes for mt8173 arm64: dts: mt8173: correct cpu type of cpu2 and cpu3 to cortex-a72 dt-bindings: irq: mtk,sysirq: add support for MT8516 dt-bindings: serial: mtk-uart: add support for MT8516 dt-bindings: timer: mtk-timer: add support for MT8516 dt-bindings: wdog: mtk-wdt: add support for MT851 dt-bindings: soc: fix a typo for MT7623A dt-bindings: mediatek: update bindings for MT7629 SoC arm64: dts: mt8183: add pinctrl file dt-bindings: mtk-sysirq: Add compatible for Mediatek MT8183 arm64: dts: Using standard CCF interface to set vcodec clk Signed-off-by: Olof Johansson --- ad88400145a23e063615226f5c69e74945fe17ea diff --cc Documentation/devicetree/bindings/serial/mtk-uart.txt index bcfb13194f163,ca7e9dc830875..c6b5262eb352e --- a/Documentation/devicetree/bindings/serial/mtk-uart.txt +++ b/Documentation/devicetree/bindings/serial/mtk-uart.txt @@@ -16,7 -17,7 +17,8 @@@ Required properties * "mediatek,mt8127-uart" for MT8127 compatible UARTS * "mediatek,mt8135-uart" for MT8135 compatible UARTS * "mediatek,mt8173-uart" for MT8173 compatible UARTS + * "mediatek,mt8183-uart", "mediatek,mt6577-uart" for MT8183 compatible UARTS + * "mediatek,mt8516-uart" for MT8516 compatible UARTS * "mediatek,mt6577-uart" for MT6577 and all of the above - reg: The base address of the UART register bank.