From: Alistair Francis <alistair.francis@wdc.com>
Date: Sat, 1 Feb 2020 01:01:41 +0000 (-0800)
Subject: target/riscv: Add the Hypervisor extension
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=af1fa0039c799a350bcde07b3d8a71dfde07d11b;p=qemu.git

target/riscv: Add the Hypervisor extension

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chih-Min Chao <chihmin.chao@sifive.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
---

diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 95de9e58a2..010125efd6 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -67,6 +67,7 @@
 #define RVC RV('C')
 #define RVS RV('S')
 #define RVU RV('U')
+#define RVH RV('H')
 
 /* S extension denotes that Supervisor mode exists, however it is possible
    to have a core that support S mode but does not have an MMU and there