From: William Qiu Date: Fri, 22 Sep 2023 06:28:34 +0000 (+0800) Subject: riscv: dts: starfive: add assigned-clock* to limit frquency X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=af571133f7ae028ec9b5fdab78f483af13bf28d3;p=linux.git riscv: dts: starfive: add assigned-clock* to limit frquency In JH7110 SoC, we need to go by-pass mode, so we need add the assigned-clock* properties to limit clock frquency. Signed-off-by: William Qiu Reviewed-by: Emil Renner Berthing Signed-off-by: Conor Dooley --- diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index c4f389a9309b9..5cdecbfa67c0b 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -250,6 +250,8 @@ &mmc0 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <8>; cap-mmc-highspeed; mmc-ddr-1_8v; @@ -266,6 +268,8 @@ &mmc1 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <4>; no-sdio; no-mmc;