From: Thierry Reding <treding@nvidia.com>
Date: Fri, 2 Sep 2022 15:05:29 +0000 (+0200)
Subject: arm64: tegra: Fixup iommu-map property formatting
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b0c1a994f66050034c970a8187d88d4e1283f9d9;p=linux.git

arm64: tegra: Fixup iommu-map property formatting

Make sure that each phandle-array is enclosed in a set of angular
brackets and properly indent each entry.

Signed-off-by: Thierry Reding <treding@nvidia.com>
---

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 59a10fb184f82..526272f76637a 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1485,15 +1485,14 @@
 		iommus = <&smmu TEGRA186_SID_HOST1X>;
 
 		/* Context isolation domains */
-		iommu-map = <
-			0 &smmu TEGRA186_SID_HOST1X_CTX0 1
-			1 &smmu TEGRA186_SID_HOST1X_CTX1 1
-			2 &smmu TEGRA186_SID_HOST1X_CTX2 1
-			3 &smmu TEGRA186_SID_HOST1X_CTX3 1
-			4 &smmu TEGRA186_SID_HOST1X_CTX4 1
-			5 &smmu TEGRA186_SID_HOST1X_CTX5 1
-			6 &smmu TEGRA186_SID_HOST1X_CTX6 1
-			7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
+		iommu-map = <0 &smmu TEGRA186_SID_HOST1X_CTX0 1>,
+			    <1 &smmu TEGRA186_SID_HOST1X_CTX1 1>,
+			    <2 &smmu TEGRA186_SID_HOST1X_CTX2 1>,
+			    <3 &smmu TEGRA186_SID_HOST1X_CTX3 1>,
+			    <4 &smmu TEGRA186_SID_HOST1X_CTX4 1>,
+			    <5 &smmu TEGRA186_SID_HOST1X_CTX5 1>,
+			    <6 &smmu TEGRA186_SID_HOST1X_CTX6 1>,
+			    <7 &smmu TEGRA186_SID_HOST1X_CTX7 1>;
 
 		dpaux1: dpaux@15040000 {
 			compatible = "nvidia,tegra186-dpaux";
diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index d0ed55e5c8607..ed2fd951122b1 100644
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1869,15 +1869,14 @@
 			iommus = <&smmu TEGRA194_SID_HOST1X>;
 
 			/* Context isolation domains */
-			iommu-map = <
-				0 &smmu TEGRA194_SID_HOST1X_CTX0 1
-				1 &smmu TEGRA194_SID_HOST1X_CTX1 1
-				2 &smmu TEGRA194_SID_HOST1X_CTX2 1
-				3 &smmu TEGRA194_SID_HOST1X_CTX3 1
-				4 &smmu TEGRA194_SID_HOST1X_CTX4 1
-				5 &smmu TEGRA194_SID_HOST1X_CTX5 1
-				6 &smmu TEGRA194_SID_HOST1X_CTX6 1
-				7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
+			iommu-map = <0 &smmu TEGRA194_SID_HOST1X_CTX0 1>,
+				    <1 &smmu TEGRA194_SID_HOST1X_CTX1 1>,
+				    <2 &smmu TEGRA194_SID_HOST1X_CTX2 1>,
+				    <3 &smmu TEGRA194_SID_HOST1X_CTX3 1>,
+				    <4 &smmu TEGRA194_SID_HOST1X_CTX4 1>,
+				    <5 &smmu TEGRA194_SID_HOST1X_CTX5 1>,
+				    <6 &smmu TEGRA194_SID_HOST1X_CTX6 1>,
+				    <7 &smmu TEGRA194_SID_HOST1X_CTX7 1>;
 
 			nvdec@15140000 {
 				compatible = "nvidia,tegra194-nvdec";