From: Lei Wang <lei4.wang@intel.com>
Date: Wed, 24 Apr 2024 07:29:12 +0000 (-0400)
Subject: target/i386: Introduce SapphireRapids-v3 to add missing features
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b10b2481738304db13d28252e86c10555121a5b3;p=qemu.git

target/i386: Introduce SapphireRapids-v3 to add missing features

Add the missing features(ss, tsc-adjust, cldemote, movdiri, movdir64b) in
the SapphireRapids-v3 CPU model.

Signed-off-by: Lei Wang <lei4.wang@intel.com>
Message-ID: <20240424072912.43188-1-lei4.wang@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa3b2d8391..e5723f232c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3970,6 +3970,17 @@ static const X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "ss", "on" },
+                    { "tsc-adjust", "on" },
+                    { "cldemote", "on" },
+                    { "movdiri", "on" },
+                    { "movdir64b", "on" },
+                    { /* end of list */ }
+                }
+            },
             { /* end of list */ }
         }
     },