From: Peter Geis <pgwipeout@gmail.com>
Date: Wed, 11 May 2022 15:01:17 +0000 (-0400)
Subject: arm64: dts: rockchip: enable sfc controller on Quartz64 Model A
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b181a1e8b3ffc0b4d723245765ead3ac5f32e308;p=linux.git

arm64: dts: rockchip: enable sfc controller on Quartz64 Model A

Add the sfc controller binding for the Quartz64 Model A. This is not
populated by default, so leave it disabled.

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20220511150117.113070-7-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index a3f9b949643c7..a02ac75916f40 100644
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -617,6 +617,22 @@
 	status = "okay";
 };
 
+&sfc {
+	pinctrl-0 = <&fspi_pins>;
+	pinctrl-names = "default";
+	#address-cells = <1>;
+	#size-cells = <0>;
+	status = "disabled";
+
+	flash@0 {
+		compatible = "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <24000000>;
+		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <1>;
+	};
+};
+
 /* spdif is exposed on con40 pin 18 */
 &spdif {
 	status = "okay";