From: Joel Stanley <joel@jms.id.au>
Date: Fri, 24 Jul 2020 02:30:35 +0000 (+0930)
Subject: ARM: dts: aspeed: rainier: Add CFAM reset GPIO
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b23b2b842002424147b820f22d52a8306bd7b2ac;p=linux.git

ARM: dts: aspeed: rainier: Add CFAM reset GPIO

The GPIO on Q0 is used for resetting the CFAM of the processor that the
ASPEED master is connected to.

The signal is wired as active high on the first pass systems.

Reviewed-by: Andrew Jeffery <andrew@aj.id.au>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---

diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
index ac7cc96a15d3e..e91f3bc7a0c27 100644
--- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts
@@ -125,6 +125,12 @@
 	#address-cells = <2>;
 	#size-cells = <0>;
 
+	/*
+	 * CFAM Reset is supposed to be active low but pass1 hardware is wired
+	 * active high.
+	 */
+	cfam-reset-gpios = <&gpio0 ASPEED_GPIO(Q, 0) GPIO_ACTIVE_HIGH>;
+
 	cfam@0,0 {
 		reg = <0 0>;
 		#address-cells = <1>;