From: Joel Stanley Date: Thu, 16 Aug 2018 13:05:29 +0000 (+0100) Subject: aspeed_sdmc: Set 'cache initial sequence' always true X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b33f1e0b8921c95d744880e9f963b16a00653cad;p=qemu.git aspeed_sdmc: Set 'cache initial sequence' always true The SDRAM training routine sets the 'Enable cache initial' bit, and then waits for the 'cache initial sequence' to be done. Have it always return done, as there is no other side effects that the model needs to implement. This allows the upstream u-boot training to proceed on the ast2500-evb board. Signed-off-by: Joel Stanley Reviewed-by: Cédric Le Goater Tested-by: Cédric Le Goater Message-id: 20180807075757.7242-4-joel@jms.id.au Signed-off-by: Peter Maydell --- diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 24fd4aee2d..9ece545c4f 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -226,6 +226,7 @@ static void aspeed_sdmc_realize(DeviceState *dev, Error **errp) s->ram_bits = ast2500_rambits(s); s->fixed_conf = ASPEED_SDMC_HW_VERSION(1) | ASPEED_SDMC_VGA_APERTURE(ASPEED_SDMC_VGA_64MB) | + ASPEED_SDMC_CACHE_INITIAL_DONE | ASPEED_SDMC_DRAM_SIZE(s->ram_bits); break; default: