From: Inochi Amaoto <inochiama@outlook.com>
Date: Mon, 28 Aug 2023 04:30:22 +0000 (+0800)
Subject: riscv: dts: allwinner: d1: Add PMU event node
X-Git-Url: http://git.maquefel.me/?a=commitdiff_plain;h=b3eaec0789d87b4d6c01decf8a1f93f873619475;p=linux.git

riscv: dts: allwinner: d1: Add PMU event node

D1 has several pmu events supported by opensbi.
These events can be used by perf for profiling.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Link: https://dl.linux-sunxi.org/D1/Xuantie_C906_R1S0_User_Manual.pdf
Link: https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/pmu/rtl/aq_hpcp_top.v#L657
Reviewed-by: Guo Ren <guoren@kernel.org>
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/IA1PR20MB49534918FCA69399CE2E0C53BBE0A@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
---

diff --git a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
index 0917b18656a28..0856f18dc3cfa 100644
--- a/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
@@ -72,4 +72,43 @@
 			#interrupt-cells = <2>;
 		};
 	};
+
+	pmu {
+		compatible = "riscv,pmu";
+		riscv,event-to-mhpmcounters =
+			<0x00003 0x00003 0x00000008>,
+			<0x00004 0x00004 0x00000010>,
+			<0x00005 0x00005 0x00000200>,
+			<0x00006 0x00006 0x00000100>,
+			<0x10000 0x10000 0x00004000>,
+			<0x10001 0x10001 0x00008000>,
+			<0x10002 0x10002 0x00010000>,
+			<0x10003 0x10003 0x00020000>,
+			<0x10019 0x10019 0x00000040>,
+			<0x10021 0x10021 0x00000020>;
+		riscv,event-to-mhpmevent =
+			<0x00003 0x00000000 0x00000001>,
+			<0x00004 0x00000000 0x00000002>,
+			<0x00005 0x00000000 0x00000007>,
+			<0x00006 0x00000000 0x00000006>,
+			<0x10000 0x00000000 0x0000000c>,
+			<0x10001 0x00000000 0x0000000d>,
+			<0x10002 0x00000000 0x0000000e>,
+			<0x10003 0x00000000 0x0000000f>,
+			<0x10019 0x00000000 0x00000004>,
+			<0x10021 0x00000000 0x00000003>;
+		riscv,raw-event-to-mhpmcounters =
+			<0x00000000 0x00000001 0xffffffff 0xffffffff 0x00000008>,
+			<0x00000000 0x00000002 0xffffffff 0xffffffff 0x00000010>,
+			<0x00000000 0x00000003 0xffffffff 0xffffffff 0x00000020>,
+			<0x00000000 0x00000004 0xffffffff 0xffffffff 0x00000040>,
+			<0x00000000 0x00000005 0xffffffff 0xffffffff 0x00000080>,
+			<0x00000000 0x00000006 0xffffffff 0xffffffff 0x00000100>,
+			<0x00000000 0x00000007 0xffffffff 0xffffffff 0x00000200>,
+			<0x00000000 0x0000000b 0xffffffff 0xffffffff 0x00002000>,
+			<0x00000000 0x0000000c 0xffffffff 0xffffffff 0x00004000>,
+			<0x00000000 0x0000000d 0xffffffff 0xffffffff 0x00008000>,
+			<0x00000000 0x0000000e 0xffffffff 0xffffffff 0x00010000>,
+			<0x00000000 0x0000000f 0xffffffff 0xffffffff 0x00020000>;
+	};
 };